The invention relates to an apparatus for decoding a serial datastream of channel words into a datastream of information words. Such apparatus is well known in the art. Reference is made in this respect to U.S. Pat. No. 5,477,222 (PHN 14448).
The known apparatus requires a decoding processing speed in relation to the bitrate of the serial datastream received. Especially with increasing bitrates, this requires complex and expensive electronic circuitry.
The invention aims at providing an improved decoder apparatus which is capable of decoding serial datastreams of relatively high bitrates with a relatively simple electronic circuitry. The apparatus in accordance with the invention comprises an apparatus for decoding a serial datastream of channel words into a datastream of information words, the apparatus comprising input means for receiving the serial data stream of channel words,
serial-parallel conversion means for serial-to-parallel conversion of the serial datastream into a parallel datastream of n-bit intermediate channel words, where n is a positive integer value, clock signal generation means for deriving a first clock signal of a specific frequency from the serial datastream of channel words,
frequency division means for dividing the frequency of the clock signal generated by the generation means by a factor of n/a, so as to obtain a second clock signal of a reduced frequency, where a is a positive constant value,
sync word detection means for detecting sync words present in said serial datastream of channel words, said sync word detection means being adapted to receive said n-bit intermediate channel words from said serial-parallel conversion means under the influence of said second clock signal, said sync word detection means further being adapted to generate an offset control signal, said offset control signal being indicative of the relative offset, given in numbers of bits, between the start of a sync word and the location of this start position within an n-bit intermediate channel word,
converter means for converting said n-bit intermediate channel words into n-bit phase shifted channel words and for converting said phase shifted channel words into information words in response to said second clock signal and said offset signal.
The invention is based on the following recognition. Serial-to-parallel conversion results in accordance with the invention in a parallel datastream of n-bit intermediate channel words. When applying the decoding apparatus in accordance with the invention in the parity preserving decoding apparatus as described in U.S. Pat. No. 5,477,222, in which groups of 3-bit channel words are converted into groups of 2-bit information words, n could be chosen equal to 3. Further, by dividing the frequency of the first clock signal by n, the signal processing speed on the parallel datastream of n-bit channel words is lowered by a factor of n, so that less stringent requirements on the signal processing circuitry are required. A simple integration into an IC is possible. Further, a low power consumption is the result.
It is to be noted that GB 1,540,617 discloses a decoding apparatus provided with a serial-to-parallel converter and a frequency divider. However, the known decoder apparatus does not disclose a sync detector which functions in the reduced clock frequency domain.